The relative impact of manufacturing variations to the performance of integrated circuits increases dramatically from technology node to technology node. Extensive research has been commenced recently to improve timing analysis capabilities as a means of compensating for manufacturing variations.
Critical dimensions are scaling faster than our control of them. Thus, the variability of physical dimensions, such as the effective length of a transistor channel, is proportionately increasing.
In previous technologies, variability was dominated by the front-end-of-the-line, or active transistors and gates. With recent technology generations, the back-end-of-the-line or interconnect metallization has also shown large variability. These sources of variability are not correlated to the former, and further not correlated from one metal level to another due to differences in geometry and metallurgy from layer to layer.
The variation of the different parameters can be split into two major components. The first component is the deviation from the average for one particular chip, which may be characterized as local variation. The second component is the deviation of the average over different chips, which is known as global variation. FIG. 1 shows a schematic diagram with a probability distribution 10 of the local variations and a probability distribution 12 of the global variations. In FIG. 1, point A is the left end point of the local variation 10, point B is the right end point of the local variation 10, C is the left end point of the global variation 12 and D is the right end point of the global variation 12.
While analyzing, for example setup timing on a single chip, the smaller spread of the local variation 10 shown in FIG. 1 is assumed. The larger spread of the global variation 12 will not occur on the same chip. However, it is not known, where the center point of the distribution is located, of the local variation 10 relative to the global variation 12.
A worst case is explained by the following example. The semiconductor chip comprises a number n of several layers i. The layers i=2, i=3 and i=5 exhibit relatively slow performance because the interconnect geometries are smaller and the wiring density is greater relative to higher metal layers. Layer i=6 contains wide metal interconnect wires and will exhibit higher performance characteristics relative to lower metal layers. The data path logic is wired on layers i=2 and i=3. The launching clock path uses layer i=5 and the receiving clock path uses layer i=6. If a data path using layers i=2 and i=3 is launched by the latch receiving the clock signal of layer i=5 and if the same data path is received by the latch receiving the clock signal of layer i=6, the data signal arrives after the clock signal, since the launching clock path and data path are slow and the receiving clock path is fast. A setup violation can readily occur under this worst case scenario. Such timing violations may occur with a certain probability, if the parameters influencing the launching and receiving path are independent. In this case one parameter may be on the left most tail of the distribution in FIG. 1 and the other on the right most tail. If the data path was routed mostly using the metallization of the receiving clock path on the layer i=6, there could still be a variation in delay for the data path relative to the receiving clock path, but with a much smaller local variation 10.
Static timing analysis is a very powerful and widely used method to analyze the timing quality of a chip design. Circuit and wiring delays are propagated through the logic network and compared to required arrival times at certain test points, usually clocked registers or outputs. The delay of the circuit is given as the function of the input slew, the output capacitive load and environmental factors affecting performance, such as voltage and temperature. The actual delay varies on each individual chip, as shown in the local variation 10 in the probability distribution of FIG. 1. The average delay varies from chip to chip, as shown in the global variation 12 in the probability distribution of FIG. 1. Several manufacturing parameters influence the electrical properties of the design and hence the delay, including transistor channel width as well as spacing and width of interconnect wires on each metal layer.
Several simplifications are known. It is assumed that the worst or best case delay occurs at the extreme points of the distribution shown in FIG. 1. This means that it is sufficient to analyze the timing for all variations of the two extreme points of the distribution for each variable. In other words if there are k parameters x, there are 2^k different combinations of the parameters x that need to be analyzed. A typical value would be k=10.
With the approaches of the prior art, the layer assignment of the data path in the logic circuit does not consider variation at all. It is either controlled by wiring and congestion, by timing criteria not considering variations, or purely accidental.
The paper “Death, Taxes and Failing Chips” by Chandu Visweswariah (DAC 2003), incorporated herein by reference, describes the problems of manufacturing variations relating to the design of high-performance integrated circuits. In particular this paper pays attention to statistical timing analysis and enumerates desirable attributes that would render such an analysis capability.
The paper “First-Order Incremental Block-Based Statistical Timing Analysis” by Chandu Visweswariah et. al. (DAC 2004), incorporated herein by reference, describes a canonical first order delay model, that takes into account both correlated and independent randomness. In particular a statistical timing algorithm is disclosed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources are available.